The present invention relates to a current source device, an oscillator device and a pulse generator used in a semiconductor integrated circuit or the like.
A current source device configured as a basic circuit block is used in a semiconductor integrated circuit. The current source device supplies a predetermined current determined according to circuit constants to other circuit blocks or the like. A circuit example of a conventional current source device 100 is shown in FIG. 1. The current source device 100 comprises a reference voltage generating unit 110, a drive unit 120 and an output unit 130. The reference voltage generating unit 110 generates a reference voltage VREF for determining an output current by dividing a source voltage VCC with resistors. Incidentally, the reference voltage VREF is VREF=VCC·R12/(R11+R12) in the circuit shown in FIG. 1. The reference voltage VREF is supplied to an inversion input terminal of an operational amplifier OP1 of the drive unit 120. An output terminal of the operational amplifier OP1 is connected to the gate of a PMOS transistor P11. The source of the PMOS transistor P11 is connected to the source voltage VCC and the drain thereof is connected to a resistor R13 whose one end is grounded. A potential developed at a connecting point of the drain of the PMOS transistor P11 (first FET) and the resistor R13 is connected to a non-inversion input terminal of the operational amplifier OP1. A PMOS transistor P12 (second FET) is connected to a gate line of the PMOS transistor P11. The source of the PMOS transistor P12 is connected to the source voltage VCC and the drain thereof is connected to its corresponding drain of an NMOS transistor N12 (third FET). Namely, the NMOS transistor N12 is connected in series with the PMOS transistor P12. The gate and drain of the NMOS transistor N12 are short-circuited to each other and the source thereof is grounded. Here, a current Ill that flows through the PMOS transistor P11 can be represented as I11=VREF/R13. On the other hand, if each transistor is used in a saturated region, then a relationship of I12∝I11 is established between the current I11 and a current I12 that flows through the PMOS transistor P12 and the NMOS transistor N12. A voltage VBP developed at a gate line for the PMOS transistors P11 and P12 is used as a gate voltage of a PMOS transistor P13 of the output unit 130, and a voltage VBN developed at a gate line for the NMOS transistor N12 is used as gate voltage of an NMOS transistor N13 of the output unit 130. The source of the PMOS transistor P13 of an output stage is connected to the source voltage VCC and the drain thereof serves as an output terminal OUT1. The source of the NMOS transistor N13 of the output stage is grounded and the drain thereof serves as an output terminal OUT2. With the connection of anther circuit block or the like between the output terminals OUT1 and OUT2 in the current source device 100 having such a configuration, a drive current corresponding to the reference voltage VREF can be supplied to the corresponding circuit block or the like. The current source device referred to above can be used as, for example, a drive current source of an oscillator device having a ring oscillator circuit comprised of inverter circuits of odd-numbered stages. In this case, drive currents are supplied from the current source device every plural inverter circuits constituting the ring oscillator circuit. The current source device can also be used as, for example, a drive current source of a pulse generator including a delay circuit comprised of inverter circuits of plural stages. Even in this case, drive currents are supplied from the current source device every plural inverter circuits constituting the delay circuit.
The above prior art refers to a patent document 1 (Japanese Unexamined Patent Publication No. 2000-78510).
In the above current source device, the condition for its normal operation is that the drive voltages VBP and VBN for driving the PMOS transistor P13 and NMOS transistor N13 of the output stage are respectively set to predetermined potentials. On the other hand, the setting of an output current in a halt state of the current source device to zero might be required depending on specs. In this case, however, it is considered that the drive voltage VBP of the PMOS transistor P13 of the output stage is set to the source voltage VCC to cut off the output current. Further, in this case, it is considered that VBN is set to a ground potential to avoid that the drive voltage VBN of the NMOS transistor N13 of the output stage reaches an indefinite voltage. Thus, there is a need to change the drive voltages VBP and VBN of the transistors of the output stage from the source voltage VCC or ground potential to predetermined potentials when the current source device is started from its halt state. It cannot be however expected that a desired output current is obtained during a period of transition made until VBP and VBN reach a predetermined voltage respectively. Namely, the period during which the required output current cannot be obtained exists immediately after the start-up of the current source device. Thus, in the oscillator device using the current source device as the drive current source as described above, a normal frequency output cannot be expected during a period taken until the output current reaches a predetermined value, after the start-up of the current source device. In the pulse generator using the current source device as the drive current source as mentioned above, a normal pulse output cannot be expected during a period taken until the output current reaches a predetermined value, after the start-up of the current source device.